Lateral BiCMOS replacement metal gate

ABSTRACT

A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first CMOS device and within a second recess located between sidewall spacers of a second CMOS device. A dummy titanium nitride layer is deposited on the high-k dielectric layer. Next, the high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess in the second CMOS device. A silicon cap layer is deposited within the first recess and the second recess, the silicon cap layer is located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device. Subsequently, dopants are implanted into the silicon cap layer located in the second recess of the second CMOS device.

BACKGROUND

The present invention generally relates to semiconductor devices, and more particularly, to bipolar complementary metal-oxide-semiconductor (BiCMOS) devices.

Complementary metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FETs) as part of advanced integrated circuits (IC), such as CPUs, memory, storage devices, and the like. At the core of planar FETs, a channel region is formed in an N-doped or P-doped semiconductor substrate on which a gate structure is formed. The overall fabrication process includes forming a gate structure over a channel region connecting a source-drain region within the substrate on opposite ends of the gate, typically with some vertical overlap between the gate and the source and drain region.

Bipolar junction transistor (BJT) technology may be typically found in demanding types of integrated circuits, especially integrated circuits for high-frequency applications. One high-frequency application for BJTs is in radiofrequency integrated circuits (RFICs), which are used in wireless communications systems, power amplifiers in cellular telephones, and other types of high speed integrated circuits. Conventional BJTs are three-terminal electronic devices that include three semiconductor regions, namely an emitter, a base, and a collector. Generally, a BJT includes a pair of p-n junctions, namely a collector-base junction and an emitter-base junction. A voltage applied across the emitter-base junction of a BJT controls the movement of charge carriers that produce charge flow between the collector and emitter regions of the BJT.

An NPN bipolar junction transistor includes two regions of N-type semiconductor material constituting the emitter and collector, and a region of P-type semiconductor material located between the two regions of n-type semiconductor material to constitute the base. A PNP bipolar junction transistor has two regions of P-type semiconductor material constituting the emitter and collector, and a region of N-type semiconductor material located between two regions of P-type semiconductor material to constitute the base.

BJTs may also be combined with CMOS field effect transistors in bipolar complementary metal-oxide-semiconductor (BiCMOS) integrated circuits, which take advantage of the positive characteristics of both transistor types in the construction of the integrated circuit.

Scaling down of CMOS FETs dimensions requires a high-k metal gate to reduce gate leakage and improve device performance. A polycristalline silicon material, commonly referred as polysilicon or poly, is normally used in the gate manufacturing process. Polysilicon exhibits high thermal resistivity, which makes a polysilicon gate resistant to high temperature processes such as high temperature annealing. The replacement of a polysilicon gate with a metal gate electrode is frequently used in CMOS fabrication to address problems related to high temperature processing on metal materials. This process is known as replacement metal gate (RMG) or gate last process. A RMG process includes the formation of a dummy polysilicon gate structure, commonly referred to as a dummy poly gate or simply a dummy gate, in the semiconductor substrate. The device manufacturing may continue until deposition of an interlayer dielectric (ILD) layer. After the ILD layer deposition, the dummy gate may be removed and replaced with a high-k metal gate.

Improved RMG processes integrating BiCMOS transistor technology may facilitate advancing the capabilities of current high-k device technology.

SUMMARY

According to one embodiment of the present disclosure, a method of forming a semiconductor structure includes: depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first CMOS device and within a second recess located between sidewall spacers of a second CMOS device, depositing a dummy titanium nitride layer on the high-k dielectric layer, removing the high-k dielectric layer and the dummy titanium nitride layer from the second recess in the second CMOS device without removing the high-k dielectric and dummy titanium nitride layers from the first recess in the first CMOS device, depositing a silicon cap layer to fill the first recess and the second recess, the silicon cap layer being located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device and

implanting dopants into the silicon cap layer located in the second recess of the second CMOS device without implanting dopants into the silicon cap layer in the first recess of the first CMOS device.

According to another embodiment of the present disclosure, a method of forming a semiconductor structure includes: forming a first CMOS device in a first region of a semiconductor substrate having a first dummy gate formed between first sidewall spacers and above a SOI layer of the semiconductor substrate, forming a second CMOS device in a second region of the semiconductor substrate having a second dummy gate formed between second sidewall spacers and above the SOI layer of the semiconductor substrate, removing the first dummy gate and the second dummy gate to form a first recess and a second recess, the first and second recesses being located between the first and second sidewall spacers respectively,

depositing a high-k dielectric layer within the first recess and within the second recess, depositing a dummy titanium nitride layer on the high-k dielectric layer, removing the high-k dielectric layer and the dummy titanium nitride layer from the second recess in the second CMOS device without removing the high-k dielectric and dummy titanium nitride layers from the first recess in the first CMOS device, depositing a silicon cap layer within the first recess and the second recess, the silicon cap layer fills the first and second recesses and is located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device, implanting dopants into the silicon cap layer in the second recess of the second CMOS device without implanting dopants into the silicon cap layer in the first recess of the first CMOS device and forming a metal gate on top of the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device.

According to another embodiment of the present disclosure, a semiconductor structure includes: a CMOS device in a first region of a semiconductor substrate having a metal gate formed between first sidewall spacers and above a high-k dielectric layer and a dummy titanium nitride layer, the metal gate being located above a channel region connecting a source-drain region within the semiconductor substrate, a BJT device in a second region of the semiconductor substrate having a base region formed between second sidewall spacers and an emitter-collector region adjacent to the base region, a cap layer located above the semiconductor substrate, an ILD layer located above the cap layer and between the CMOS and BJT devices and a plurality of contacts formed in the ILD layer.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view of a semiconductor structure depicting an intermediate step during a replacement metal gate process, according to an embodiment of the present disclosure;

FIG. 2 is a cross-sectional view of a semiconductor structure depicting the removal of dummy gates from the CMOS devices in the semiconductor substrate, according to an embodiment of the present disclosure;

FIG. 3 is a cross-sectional view of a semiconductor structure depicting the formation of a high-k dielectric layer and a dummy titanium nitride layer in recesses formed after removing the dummy gates, according to an embodiment of the present disclosure;

FIG. 4 is a cross-sectional view of a semiconductor structure depicting masking an NMOS and a PMOS sub-region of the semiconductor substrate in order to protect this area and remove the high-k dielectric and dummy titanium nitride layers from a NPN BJT and PNP BJT sub-regions of the semiconductor substrate, according to an embodiment of the present disclosure;

FIG. 5 is a cross-sectional view of a semiconductor structure depicting the deposition of a silicon cap layer in the CMOS and BJT regions of the semiconductor substrate, according to an embodiment of the present disclosure;

FIG. 6 is a cross-sectional view of a semiconductor structure depicting an ion implantation technique being conducted on the NPN BJT region of the semiconductor substrate, according to an embodiment of the present disclosure;

FIG. 7 is a cross-sectional view of a semiconductor structure depicting an ion implantation technique being conducted on the PNP BJT region of the semiconductor substrate, according to an embodiment of the present disclosure;

FIG. 8 is a cross-sectional view of a semiconductor structure depicting the removal of the silicon cap layer from the NMOS and PMOS devices, according to an embodiment of the present disclosure;

FIG. 9 is a cross-sectional view of a semiconductor structure depicting the formation of a metal gate in the NMOS and PMOS devices, according to an embodiment of the present disclosure; and

FIG. 10 is a cross-sectional view of a semiconductor structure depicting the formation of silicided contacts in the semiconductor structure, according to an embodiment of the present disclosure.

The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements.

DETAILED DESCRIPTION

Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. This invention may, however, be modified in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessary obscuring the presented embodiments.

One method of manufacturing a BiCMOS structure is described in detail below by referring to the accompanying drawings in FIGS. 1-10, in accordance with illustrative embodiments of the present disclosure. More specifically, the method may include integrating a CMOS replacement metal gate (RMG) process flow with formation of bipolar junction transistors (BJTs).

Referring to FIG. 1, a cross-sectional view of a planar CMOS semiconductor structure 100 is shown at an intermediate step during a replacement metal gate (RMG) process flow. At this step of the RMG process, the semiconductor structure 100 may be generally complete with a dummy gate 116 formed over a semiconductor-on-insulator (SOI) substrate 105. It should be noted that the dummy gate 116 may be formed in any semiconductor substrate know to a person having ordinary skill in the art, including but not limited to SOI substrates and bulk silicon substrates. Also, it should be noted that while this description refers to some components of the semiconductor structure 100 in the singular tense, more than one component may be depicted throughout the figures and like components are labeled with like numerals.

The SOI substrate 105 employed in the present embodiment may include a base substrate 102, a buried dielectric layer 104 (e.g., buried oxide) formed on top of the base substrate 102, and a SOI layer 106 formed on top of the buried dielectric layer 104. The buried dielectric layer 104 isolates the SOI layer 106 from the base substrate 102. The base substrate 102 may be made from any of several known semiconductor materials such as, for example, silicon, germanium, silicon-germanium alloy, silicon carbide, silicon-germanium carbide alloy, and compound (e.g. III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide. Typically the base substrate 102 may be about, but is not limited to, several hundred microns thick. For example, the base substrate 102 may include a thickness ranging from 0.5 mm to about 1.5 mm.

The buried dielectric layer 104 may be formed from any of several known dielectric materials. Non-limiting examples include, for example, oxides, nitrides and oxynitrides of silicon. Oxides, nitrides and oxynitrides of other elements are also envisioned. In addition, the buried dielectric layer 104 may include crystalline or non-crystalline dielectric material. Moreover, the buried dielectric layer 104 may be formed using any of several known methods. Non-limiting examples include ion implantation methods, thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods and physical vapor deposition methods. Alternatively, the buried dielectric layer 104 may include a thickness ranging from about 10 nm to about 500 nm. In one embodiment, the buried dielectric layer 104 may be about 150 nm thick.

The SOI layer 106 may include any of the several semiconductor materials included in the base substrate 102. In general, the base substrate 102 and the SOI layer 106 may include either identical or different semiconductor materials with respect to chemical composition, dopant concentration and crystallographic orientation. In one particular embodiment of the present invention, the base substrate 102 and the SOI layer 106 may include semiconductor materials with different crystallographic orientations. The SOI layer 106 may include a thickness ranging from about 5 nm to about 100 nm. Methods for forming the SOI layer 106 are well known in the art. Non-limiting examples include SIMOX (Separation by Implantation of Oxygen), wafer bonding, and ELTRAN® (Epitaxial Layer TRANsfer).

With continued reference to FIG. 1, the semiconductor structure 100 may further include an N-type region 200 and a P-type region 300. The N-type region 200 may include an N-channel metal-oxide semiconductor (NMOS) sub-region 210 and an NPN BJT sub-region 220. The NMOS sub-region 210 may include an NMOS device 212. At this point of the manufacturing process, the NPN BJT sub-region 220 may also include an NMOS device 212 that may be converted in subsequent steps (described below) to an NPN BJT device.

Similarly, the P-type region 300 may include a P-channel metal-oxide semiconductor (PMOS) sub-region 310 and a PNP BJT sub-region 320. The PMOS sub-region 310 may include a PMOS device 312. At this point of the manufacturing process, the PNP BJT sub-region 320 may also include a PMOS device 312 that may be converted in subsequent steps (described below) to a PNP BJT device.

The process of forming NMOS and PMOS devices is very well known in the art and generally may include forming a gate over a channel region connecting a source-drain region within an N-doped or P-doped semiconductor substrate. It is understood that commonly NMOS and PMOS devices may be formed simultaneously within the same semiconductor substrate, and that both NMOS and PMOS devices may be used together in an integrated circuit. Typically, NMOS and PMOS devices may be separated from one another both physically and electrically by an isolation region 108. The isolation region 108 may include shallow trench isolation (STI) regions.

With continued reference to FIG. 1, the NMOS and PMOS devices 212, 312 may have a dummy gate dielectric 118 which may be formed over the SOI substrate 105 by any deposition method known in the art, for example, by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), high-density CVD (HDCVD), physical vapor deposition (PVD), plating, sputtering, evaporation, and chemical solution deposition of a dielectric material. Alternatively, the dummy gate dielectric 118 may be formed through oxidizing a top surface of the SOI substrate 105. In one embodiment, the dummy gate dielectric 118 may include a high-k dielectric material having a dielectric constant greater than, for example, 3.9, which is the dielectric constant of silicon oxide.

With continued reference to FIG. 1, the semiconductor structure 100 may further include a dummy gate 116. The dummy gate 116 may be formed using conventional techniques known in the art. For example, the dummy gate 116 may be formed by depositing a blanket layer of polysilicon.

The dummy gate 116 may include sidewall spacers 112. The sidewall spacers 112 may be formed by depositing or growing a conformal dielectric layer, followed by an anisotropic etch that removes the dielectric from the horizontal surfaces of the semiconductor structure 100, while leaving it on the sidewalls of the dummy gate 116. In a RMG process flow the sidewall spacers 112 may remain on the sidewalls of the dummy gate 116. In one embodiment, the sidewall spacers 112 may include any suitable dielectric material such as silicon nitride. In one embodiment, the sidewall spacers 112 may have a horizontal width, or thickness, ranging from about 3 nm to about 30 nm. The sidewall spacers 112 may include a single layer of dielectric material; however, multiple layers of dielectric material may also be embodied. The sidewall spacers 112 may be positioned along the sidewalls of the dummy gate 116 and separate a subsequently formed metal gate from the source-drain region.

With continued reference to FIG. 1, the semiconductor structure 100 may further include a cap layer 122 and an interlayer dielectric (ILD) layer 120 formed above the cap layer 122.

The cap layer 122 may be deposited by means of any suitable deposition method and may have a thickness ranging from about 5 nm to about 30 nm and ranges there between. The cap layer 122 may include an insulator of silicon nitride, silicon carbide or the like which may function as both a barrier, particularly when a low-k material that may be subject to diffusion of moisture is used as the ILD layer, and an etch stop.

The ILD layer 120 may be deposited above the cap layer 120 by any deposition method known in the art. The ILD layer 120 may have a thickness ranging from about 30 nm to about 100 nm and ranges there between. The ILD layer 120 may include: silicon oxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide or any other suitable dielectric material that may fill the gaps between dummy gates 116 and other existing devices within the semiconductor substrate 110.

Referring now to FIG. 2, the dummy gate 116 and the dummy gate dielectric 118 shown in FIG. 1 may be removed from the NMOS devices 212 in the N-type region 200 and from the PMOS devices 312 in the P-type region 300. The dummy gate 116 (FIG. 1) and dummy gate dielectric 118 (FIG. 1) may be removed selective to the sidewall spacers 112 by any suitable etching technique known in the art. For example, the dummy gate 116 (FIG. 1) and dummy gate dielectric 118 (FIG. 1) may be selectively etched by means of a wet etch process or a combination of wets and reactive ion etching (RIE).

Etching of the dummy gate 116 (FIG. 1) and dummy gate dielectric 118 (FIG. 1) may create recesses 113 between adjacent sidewall spacers 112. Such recesses may be used in subsequent steps to form an NPN BJT device in sub-region 220 and a PNP BJT device in sub-region 320 as described below. The recesses 113 in sub-region 210 and sub-region 310 may subsequently be filled with a conductive material to form a metal gate for the NMOS device 212 and PMOS device 312 as further described below.

Referring now to FIGS. 3-10 a process to integrate a RMG process flow with formation of BJT devices may be described according to an embodiment of the present disclosure.

Referring now to FIG. 3, a high-k dielectric layer 130 may be conformally deposited on the recesses 113 by any suitable deposition technique known in the art, for example: by atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), high-density CVD (HDCVD), physical vapor deposition (PVD), plating, sputtering, evaporation, and chemical solution deposition of a high-k dielectric material. The high-k dielectric layer 130 may include a thickness ranging from about 1 nm to about 5 nm. In one embodiment, the high-k dielectric layer 130 may include a high-k dielectric material having a dielectric constant greater than, for example, 3.9, which is the dielectric constant of silicon oxide. The high-k dielectric layer 130 may be required to fulfill the scalability and current-leakage prevention needs of the NMOS and PMOS devices 212,312.

Following the deposition of the high-k dielectric layer 130, a second conformal layer 132 (hereafter referred to as “dummy titanium nitride layer”) may be deposited on top of the high-k dielectric layer 130 by any suitable deposition method known in the art. The dummy titanium nitride layer 132 may include a thickness ranging from about 3 nm to about 10 nm. In one embodiment, the dummy titanium nitride layer 132 may include titanium nitride, titanium carbide, tantalum nitride or other suitable material.

After depositing the high-k dielectric layer 130 and the dummy titanium nitride layer 132, the semiconductor structure 100 may be subjected to a planarization process to remove excess material from the top of the semiconductor structure 100. The planarization process may be conducted using any polishing technique known in the art such as for example: chemical mechanical polishing (CMP).

Referring now to FIG. 4, a first photoresist mask 140 may be formed to cover the NMOS and PMOS sub-regions 210, 310 including the NMOS devices 212 and PMOS devices 312. The first photoresist mask 140 may protect the NMOS and PMOS devices 212, 312 during the formation of NPN BJT and PNP BJT devices in the NPN and PNP BJT subs-regions 220, 320. The steps involved in masking the NMOS and PMOS sub-regions 210, 310 are well known to those skilled in the art.

Next, the high-k dielectric layer 130 and the dummy titanium nitride layer 132 may be removed from the recesses 113 in the NPN BJT sub-region 220 and the PNP BJT sub-region 320. The removal of the high-k dielectric layer 130 and the dummy titanium nitride layer 132 may occur selectively to the sidewall spacers 112 by means of any etching technique known in the art.

After removing the high-k dielectric layer 130 and the dummy titanium nitride layer 132 from the recesses 113 in the NPN BJT sub-region 220 and the PNP BJT sub-region 320, the first photoresist mask 140 may be removed by any suitable etching technique.

Referring now to FIG. 5, a silicon cap layer 134 may be deposited within the recesses 113 (FIG. 4). In the NMOS and PMOS sub-regions 210, 310, the silicon cap layer 134 may be formed on top of the dummy titanium nitride layer 132 and high-k dielectric layer 130 of the NMOS and PMOS devices 212, 312 respectively, filling the remaining space within recesses 113 (FIG. 4). In the NPN BJT and PNP BJT sub-regions 210, 310, the silicon cap layer 134 may substantially fill the recesses 113.

The silicon cap layer 134 may be formed by any deposition method known in the art, including but not limited to: ALD, CVD, PECVD, HDCVD, PVD and the like. In one embodiment of the present disclosure the silicon cap layer 134 may include an amorphous silicon (a-Si) material. In another embodiment of the present disclosure the silicon cap layer 134 may include a polycrystalline silicon (poly silicon) material. The silicon cap layer 134 may provide a medium to form a P-type or an N-type semiconductor material that may constitute an extrinsic base for the NPN BJT device or PNP BJT device respectively, as described in the steps below.

Referring now to FIG. 6, a second photoresist mask 142 may be formed to protect the NMOS, PMOS and PNP BJT sub-regions 210, 310 and 320 of the semiconductor substrate 110. At this step of the fabrication process only the NPN BJT sub-region 220 may remain unprotected. After masking the NMOS, PMOS and PNP BJT sub-regions 210, 310 and 320, an ion implantation technique may be conducted on the unprotected NPN BJT sub-region 220 as indicated by arrows 250. The ion implantation process may include the use of P-type dopants, such as boron (B), to provide the appropriate polarity to the silicon cap layer 134 (FIG. 5) located between N-type source-drain region 230 to form a P-type base region 232 and in consequence an NPN BJT device 222. The P-type silicon cap layer 232 may act as an extrinsic base that provides a low resistance contact to the silicon region underneath which is the intrinsic base of the NPN BJT 222. Here it should be noted that in BJTs the N-type source-drain region 230 may typically be referred to as an N-type emitter-collector region.

According to an embodiment of the present disclosure, the dopant concentration of boron (B) to form the P-type semiconductor material 232 may range from about 1×10¹⁸ ions/cm³ to about 9×10²⁰ ions/cm³.

At this point of the fabrication process, the second photoresist mask 142 may be removed by means of any suitable etching technique.

Referring now to FIG. 7, a third photoresist mask 144 may be formed to protect the NMOS, NPN BJT and PMOS sub-regions 210, 310 and 220 of the semiconductor substrate 110. At this step of the fabrication process only the PNP BJT sub-region 320 may remain unprotected. After masking the NMOS, NPN BJT and PMOS sub-regions 210, 310 and 220, an ion implantation technique may be conducted on the unprotected PNP BJT sub-region 320 as indicated by arrows 350. The ion implantation process may include the use of N-type dopants, such as phosphorus (P) or arsenic (As), to provide the appropriate polarity to the silicon cap layer 134 (FIG. 6) located between P-type source-drain region 330 to form an N-type base region 332 and in consequence the PNP BJT device 322. The N-type silicon cap layer 332 may act as an extrinsic base that provides a low resistance contact to the silicon region underneath which is the intrinsic base of the PNP BJT 322. Here it should be noted that in BJTs the P-type source-drain region 330 may typically be referred to as a P-type emitter-collector region.

According to an embodiment of the present disclosure, the dopant concentration of phosphorus (P) or arsenic (As) to form the N-type semiconductor 332 may range from about 1×10¹⁸ ions/cm³ to about 9×10²⁰ ions/cm³.

At this point of the fabrication process, the third photoresist mask 144 may be removed by means of any suitable etching technique.

It should be noted that the steps described above in FIGS. 4-7 include the formation of bipolar junction transistors in the corresponding P-type or N-type region of the semiconductor substrate 105 and that such steps are not characteristic of conventional RMG process. These additional steps within the RMG process flow may allow for the formation of BJTs during CMOS RMG process having the added benefit of reducing the amount of masks required in traditional BJTs fabrication thus reducing production time and improving process cost-effectiveness.

After formation of NPN BJT device 222 and PNP BJT device 322 an annealing process may be conducted over the semiconductor structure 100 to activate the dopants introduced via ion implantation and remove the crystal structure damage caused by ion irradiation. The annealing process may be conducted by any method known in the art, for example, by rapid thermal annealing (RTA) of the semiconductor structure 100. In an embodiment of the present disclosure, the annealing temperature may range from about 800° C. to about 1100° C. In an embodiment of the present disclosure, the annealing process may also work to cure the high-k dielectric layer 130 in the NMOS and PMOS devices 212, 312.

Referring now to FIG. 8, the silicon cap layer 134 (FIG. 7) may now be removed from the NMOS device 212 and PMOS device 312. In order to remove the silicon cap layer 134 from the NMOS and PMOS devices 212, 312, a fourth photoresist mask 146 may be formed on the NPN BJT and PNP BJT sub-regions 220, 320 to protect the bipolar junction transistor devices NPN BJT 222 and PNP BJT 322. Alternatively, a hardmask material may be selectively deposited on sub-regions 220, 320 to protect the NPN BJT 222 and PNP BJT 322 during removal of the silicon cap layer 134. The steps involved in masking the NPN BJT and PNP BJT sub-regions 220, 320 to protect the NPN BJT and PNP BJT devices 222, 322 are conventional and well known to those skilled in the art.

Any suitable etching technique may be used to remove the silicon cap layer 134 from the NMOS and PMOS devices 212, 312. Etching of the silicon cap layer 134 may create recesses between adjacent sidewall spacers 112 in the NMOS and PMOS devices 212, 312. Such recesses may be subsequently filled with a conductive material to form a metal gate as shown in FIG. 9.

At this point of the fabrication process, the fourth photoresist mask 146 may be removed by means of any suitable etching technique.

Referring now to FIG. 9, at this point of the fabrication process the regular RMG process may continue by forming the corresponding N-type and P-type workfunction metals in the NMOS and PMOS devices 212, 312. The N-type and P-type workfunction metals forming P-type and N-type metal gates 240, 340 may be formed by any suitable deposition process including, but not limited to CVD, PECVD, HDCVD, PVD, plating, sputtering, evaporation, and chemical solution deposition.

In one embodiment of the present disclosure, the N-type metal gate 240 for NMOS device 212 may include: titanium nitride (TiN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN) or other suitable materials.

In another embodiment of the present disclosure, the P-type metal gate 340 for PMOS device 312 may include: titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN) or other suitable materials.

After formation of the N-type and P-type metal gates 240, 340, the semiconductor structure 100 may represent a BiCMOS device. From this point forward, all the steps are conventional in CMOS fabrication including contact patterning and silicidation.

Referring now to FIG. 10, contacts may be patterned and formed in the ILD layer 120 and cap layer 122 following conventional methods in CMOS fabrication. The formation of contacts may further include salicidation of source-drain regions 230, 330. The contacts 150 may be patterned by means of a photolithography process. Following the photolithography process, areas of the ILD layer 120 and cap layer 122 may be etched to create contact holes and then a metal layer (not shown) may be deposited within the contact holes and over the entire semiconductor substrate by means of any deposition method known in the art including, for example, by CVD, PECVD, HDCVD, PVD, plating, sputtering, evaporation, and chemical solution deposition. In one embodiment of the present disclosure, the metal layer may include a nickel-platinum alloy (NiPt) where the atomic concentration of nickel (Ni) may range from about 5% to 20%. In another embodiment of the present disclosure, the metal layer may include nickel palladium (NiPd), nickel rhenium (NiRe), titanium (Ti), titanium tantalum (TiTa), titanium niobium (TiNb), or cobalt (Co). Alternatively, other metals commonly employed in salicide processing such as tantalum (Ta), tungsten (W), cobalt (Co), nickel (Ni), platinum (Pt), palladium (Pd), or alloys thereof may be employed.

After the metal layer is formed, the semiconductor structure 100 may be subjected to a thermal annealing process, using conventional processes such as, but not limited to, rapid thermal annealing (RTA). During the thermal annealing process, the metal layer reacts with the silicon present in the source-drain regions 230, 330 to form a metal silicide. After the annealing process, an etching process may be carried out to remove substantially all un-reacted metal or metal alloy of the remaining portion of the metal layer. The etching process may include a wet etching method.

The steps described above may provide a method of forming a BiCMOS structure combining the positive characteristics of CMOS and BJT technologies to enhance device performance. Furthermore, as a result of integrating the RMG process for CMOS devices with the formation of BJT devices in a shared semiconductor substrate, the number of mask required in the process may be optimized reducing production time and improving process cost-effectiveness.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. 

What is claimed is:
 1. A semiconductor structure, comprising: a CMOS device in a first region of a semiconductor substrate having a metal gate formed between first sidewall spacers and above a high-k dielectric layer and a dummy titanium nitride layer, the metal gate being located above a channel region connecting a source-drain region within and extending above the semiconductor substrate; a BJT device in a second region of the semiconductor substrate having a base region formed between second sidewall spacers and an emitter-collector region adjacent to the base region and extending above the semiconductor substrate; an insulating cap layer located above and disposed directly over sidewalls of the source-drain region and the emitter-collector region, wherein the sidewalls of the source-drain region and the emitter-collector region extend above a top surface of the semiconductor substrate; an ILD layer located directly above the insulating cap layer and between the CMOS and BJT devices; and a plurality of contacts formed in the ILD layer, wherein the high-k dielectric layer is disposed over sidewalls of the first sidewall spacers, and the dummy titanium nitride layer is separated from the first sidewall spacers by the high-k dielectric layer.
 2. The structure of claim 1, wherein the CMOS device comprises: a planar PMOS device; and a planar NMOS device.
 3. The structure of claim 1, wherein the base region of the BJT comprises: a P-doped silicon cap layer; and an N-doped silicon cap layer.
 4. The structure of claim 1, wherein the emitter-collector region of the BJT device comprises: a P-type emitter-collector region adjacent to an N-type base region; and an N-type emitter-collector region adjacent to a P-type base region.
 5. The structure of claim 1, wherein the second sidewall spacers are located over an entire sidewall surface of the base region.
 6. The structure of claim 1, wherein a bottom surface of the base region is co-planar with a bottom surface of the high-k dielectric layer.
 7. The structure of claim 1, wherein the dummy titanium nitride layer and the high-k dielectric layer are disposed between the metal gate and the first sidewall spacers.
 8. The structure of claim 1, wherein a top surface of the high-k dielectric layer is co-planar with a top surface of the dummy titanium nitride layer.
 9. The structure of claim 1, wherein a top surface of the high-k dielectric layer is co-planar with a top surface of the dummy titanium nitride layer and a top surface of the metal gate. 